1. Field of the Invention
The present invention relates to a level-shifting circuit which shifts a level of an input voltage, and input and output circuits using the level-shifting circuit.
2. Description of the Related Art
An example of a conventionally known level-shifting circuit is shown in FIG. 7. This level-shifting circuit 1 comprises: an input terminal 2; an n-channel type MOSFET N.sub.5 which has its gate connected to the input terminal 2 and its drain connected to a voltage source V.sub.DD ; a current source CS1 which has its flow-in terminal connected to a source of the n-channel type MOSFET N.sub.5 and its flow-out terminal connected to a ground potential; and an output terminal 6 which is connected at a interconnection point between the source of the n-channel type MOSFET N.sub.5 and the flow-in terminal of the current source CS1.
The current source CS1 through which a current I.sub.DS flows in this level-shifting circuit 1 is employed a constant-current source which is not affected by the manufacturing process, nor the operating temperature, nor the supply voltage.
The operations, explained next, of this level-shifting circuit are described with reference to FIG. 7.
A gate-source voltage V.sub.GS of the n-channel type MOSFET N.sub.5 when it is provided at its input terminal 2 with a high-level voltage V.sub.IN is given by the following Equation 1: EQU V.sub.GS ={2I.sub.DS /.beta.}.sup.1/2 +V.sub.T 1
where .beta.=.mu.C.sub.OX.times.W/L,
.mu. is a surface mobility (m2/volt.times.second), COX is an electrostatic capacitance per unit area of gate channel (farad), PA1 W.sub.1 is a gate channel width (m) of the n-channel MOSFET N.sub.1, and PA1 L.sub.1 is a gate channel length (m) of the n-channel MOSFET N.sub.1. PA1 the first insulated-gate transistor and the second insulated-gate transistor share a same value of a ratio of a gate channel width to a gate channel length, in such a configuration that a constant voltage may be applied to a gate of the second insulated-gate transistor. PA1 the input circuit comprises a level-shifting circuit in which a first insulated-gate transistor and a second insulated-gate transistor having a same conductivity type as the first insulated-gate transistor are interconnected to apply an input signal to a gate of the first insulated-gate transistor, in order to output an output signal obtained by shifting a level of the input signal by a desired quantity from an interconnection point between the first insulated-gate transistor and the second insulated-gate transistor; and PA1 the first insulated-gate transistor and the second insulated-gate transistor share a same value of a ratio of a gate channel width to a gate channel length, in such a configuration that a constant voltage may be applied to a gate of the second insulated-gate transistor. PA1 the input circuit comprises a level-shifting circuit in which a source of a first insulated-gate transistor and a drain of a second insulated-gate transistor having a same conductivity type as the first insulated-gate transistor are interconnected to apply an input signal to a gate of the first insulated-gate transistor, in order to output an output signal obtained by shifting a level of the input signal by a desired quantity from an interconnection point between the first insulated-gate transistor and the second insulated-gate transistor; and PA1 the first insulated-gate transistor and the second insulated-gate transistor share a same value of a ratio of a gate channel width to a gate channel length, in such a way that a constant voltage may be applied to a gate of the second insulated-gate transistor. PA1 the output circuit comprises a level-shifting circuit in which a source of a first insulated-gate transistor and a drain of a second insulated-gate transistor having a same conductivity type as the first insulated-gate transistor to apply an input signal to a gate of the first insulated-gate transistor, in order to output an output signal obtained by shifting a level of the input signal by a desired quantity from an interconnection point between the first insulated-gate transistor and the second insulated-gate transistor; and PA1 the first insulated-gate transistor and the second insulated-gate transistor share a same value of a ratio of gate channel width to a gate channel length, in such a configuration that a constant voltage may be applied to a gate of the second insulated-gate transistor.
An output voltage V.sub.OUT which appears at the output terminal 6 is given by: EQU V.sub.OUT =V.sub.IN -V.sub.GS 2
Substituting Equation 1 into Equation 2 yields: EQU V.sub.OUT =V.sub.IN -{2I.sub.DS /.beta.}.sup.1/2 -V.sub.T 3
There is also provided a small-amplitude interface input circuit which uses this level-shifting circuit. An example of it is shown in FIG. 9.
This small-amplitude interface input circuit 10 comprises: a differential amplifier circuit 12; the level-shifting circuit 1; and a comparator 14. The level-shifting circuit 1 is formed together with the following-stage comparator 14 in the same chip, which comparator 14 is supplied with a supply voltage lower than a VDD for the level-shifting circuit 1 (e.g., 1.8V for the comparator 14 versus 3V for the level-shifting circuit), so that the level-shifting circuit 1 is used to shift the level of an input signal to such a range which can be received by the comparator 14.
The differential amplifier circuit 12 comprises: input terminals 16 and 18; a resistor R3, an n-channel type MOSFET N.sub.3 which has its gate connected to the input terminal 16 and its drain connected via the resistor R.sub.3 to the voltage source V.sub.DD ; a resistor R.sub.4 ; an n-channel type MOSFET N.sub.4 which has its gate connected to the input terminal 18 and its drain connected via the resistor R.sub.4 to the voltage source V.sub.DD ; and a current source 20 which has its flow-in terminal connected to sources of the n-channel type MOSFETs N.sub.3 and N.sub.4 and its flow-out terminal connected to the ground potential.
An output terminal O4 of this differential amplifier circuit 12 (i.e., an interconnection point between the resistor R.sub.4 and the source of the n-channel type MOSFET N.sub.4) is connected to a gate of an n-channel type MOSFET N.sub.1. The level-shifting circuit 1 has the same configuration as that shown in FIG. 7. An output terminal 6 of the level-shifting circuit 1 is connected to an input (+) of the comparator 14. To a reference input (-) of the comparator 14 is connected a voltage source (not shown) which supplies a reference voltage V.sub.CP. The comparator has its output connected to a CMOS internal circuit 22.
The level-shifting circuit 1 acts to output to the comparator 14 such binary signals as corresponding to a binary value represented by two signals INA and INB (both of which are shown in FIG. 10) mutually opposite in phase and different in voltage level which are transmitted via a transmission line and received at the separate input terminals 16 and 18 of the differential amplifier circuit 12.
That is, of the signals INA and INB (both of which are shown in FIG. 10) applied separately at the input terminals 16 and 18 respectively, the signal INB which is differential-amplified at the differential amplifier circuit 12 is supplied from the output terminal 04 of the differential amplifier circuit 12 to the level-shifting circuit 12 at its input terminal 2, where the INB signal is shifted in level to such a signal V.sub.OUT 1 (which is shown in FIG. 10) that can be received by the comparator 14, and then output from the output terminal 6 of the level-shifting circuit 1.
If the output signal V.sub.OUT 1 is sequentially input as an idealistic signal having the reference voltage V.sub.CP as its center of amplitude as shown in FIG. 10 as V.sub.OUT 1S of V.sub.OUT 1, since the reference voltage V.sub.CP is applied to the comparator at its reference input (-), the comparator 14 sequentially outputs a binary signal having such a waveform as V.sub.OUT 2(1) in FIG. 10, which signal is then processed in the CMOS internal circuit 22.
Therefore, that signal processing has no inconvenience at all.
Also, an example of the small-amplitude interface input circuit is shown in FIG. 11.
This small-amplitude interface input circuit 30 comprises: a differential amplifier circuit 32; a level-shifting circuit 34; and a differential amplifier circuit 36, in such a configuration that the level-shifting circuit 34 has two level-shifting circuits, each of which has the same configuration as that shown in FIG. 7, connected separately to the output terminals O3 and O4 of the differential amplifier circuit 32. The differential amplifier circuit 32 has the same configuration as that shown in FIG. 9. The level-shifting circuit 34 is configured of two level-shifting circuits each of which is shown in FIG. 7, in such a way that a first level-shifting circuit 34.sub.1 consists of an n-channel type MOSFET N.sub.1 and a constant current source CS1.sub.1, while a second level-shifting circuit 34.sub.2 consists of an n-channel type MOSFET N.sub.2 and a constant current source CS1.sub.2.
With this, the level-shifting circuit is formed together with the following-stage differential amplifier circuit 36 in the same chip, which differential amplifier circuit 36 is supplied with a V.sub.DD lower than a voltage source for the level-shifting circuit 34 (e.g., 1.8V for the differential amplifier circuit 36 versus 3V for the level-shifting circuit 34), so that the level-shifting circuit 34 is used to shift a signal supplied to the differential amplifier circuit 36 to such a range of level that can be received by the differential amplifier circuit 36. The reason why the level-shifting circuit 34 is used in this small-amplitude interface input circuit 30 is that if the differential amplifier circuit 36 connected at the stage following the level-shifting circuit 34 is supplied with a signal having a potential of the voltage source V.sub.DD or higher (e.g., if a signal having 2.5V as its signal amplitude center as against V.sub.DD =1.8V is supplied via a bus line), it is rendered inoperative, so that to prevent such an event from occurring, a level of signals supplied to the differential amplifier circuit 36 must be shifted to such a range of level that can be received by the differential amplifier circuit 36.
Like that shown in FIG. 9, this small-amplitude interface input circuit 30 also causes the differential amplifier circuit 36 to output binary signals which correspond to binary values represented by two signals INA and INB mutually opposite in phase and different in voltage level which are received via the transmission line at the input terminals 16 and 18 of the differential amplifier circuit 32.
That is, the signals INA and INB separately applied at the input terminals 16 and 18 are amplified at the differential amplifier circuit 32 and then respectively applied at gates of the n-channel type MOSFETs N.sub.1 and N.sub.2 of the level-shifting circuit 34. Respectively from an output terminal 61 connected to an interconnection point between a source of the n-channel type MOSFET N.sub.1 and the constant current source CS1.sub.1 and an output terminal 6.sub.2 connected to an interconnection point between a source of the n-channel type MOSFET N.sub.2 and the constant current source CS1.sub.2, signals mutually opposite in phase and different in voltage level which have been shifted in level by as much as a predetermined quantity are output and applied to the (+) and (-) input terminals of the differential amplifier circuit 36 respectively.
If, in this case, the level-shifting quantity for the signal applied at the (+) input of the differential amplifier circuit 36 is idealistically the same as that for the opposite-phase signal applied at the (-) input and, therefore, two signals which are mutually opposite in phase and different in voltage level are output from the level-shifting circuit 34 and applied to the differential amplifier circuit 36 at its (+) and (-) input terminals, when a level of voltage applied at the (+) input of the differential amplifier circuit is higher than that applied at its (-) input, the differential amplifier circuit 36 provides an output having a higher voltage level and, when a voltage level applied at the (+) input of the differential amplifier circuit 36 is lower than that applied at its (-) input, the differential amplifier circuit 36 provides an output having a lower voltage level. Thus, binary signals are output from the differential amplifier circuit which correspond to binary values represented by the two signals INA and INB mutually opposite in phase and different in voltage level which are input to the differential amplifier circuit 36 at its input terminals 16 and 18. These two signals are held in an idealistic time-wise relationship with the two input signals INA and INB which are mutually opposite in phase and different in voltage level; that is, these two signals have the same signal time-axis width as that of the signals INA and INB, so that even when subjected to signal processing at the CMOS internal circuit 38, these two signals give no inconvenience at all to that signal processing.
There is also shown in FIG. 12 another example of the small-amplitude interface input circuit.
This small-amplitude interface input circuit 40 comprises a level-shifting circuit 42 and a differential amplifier circuit 36. The level-shifting circuit 42 consists of two level-shifting circuits 42.sub.1 and 42.sub.2, each of which has the same configuration as that shown in FIG. 7, in such a configuration that the first level-shifting circuit 42.sub.1 consists of an n-channel type MOSFET N.sub.1 and a constant current source CS1.sub.1 and the second level-shifting circuit 422 consists of an n-channel type MOSFET N.sub.2 and a constant current source CS1.sub.2. These two level-shifting circuits are so configured that they are provided, at their respective input terminals 2.sub.1 and 2.sub.2, with two input signals INA and INB mutually opposite in phase and different in voltage level, via the transmission line, and also that their respective output terminals 6.sub.1 and 6.sub.2 are connected to (-) and (+) inputs of the differential amplifier circuit 36 respectively.
The reason why the level-shifting circuit 42 is used in this small-amplitude interface input circuit 40 is that since the differential amplifier circuit 36 connected at the stage following the level-shifting circuit 42 is rendered inoperative if it is supplied with a signal having a potential of the voltage source V.sub.DD or higher (e.g., if it is supplied via a bus line with a signal having 2.5V as its signal amplitude center versus V.sub.DD =1.8v), the signals supplied to the differential amplifier circuit 36 must be shifted to such a range of level that can be received by that differential amplifier circuit 36.
Thus configured small-amplitude interface input circuit 40 also causes, like those shown in FIGS. 9 and 11, the differential amplifier circuit 36 to output binary signals which correspond to binary values represented by the two input signals INS and INB mutually opposite in phase and different in voltage level which are input to the level-shifting circuits 42.sub.1 and 42.sub.2 at their respective input terminals 2.sub.1 and 2.sub.2.
That is, the signals INA and INB applied to the level-shifting circuits 42.sub.1 and 42.sub.2 at their respective input terminals 2.sub.1 and 2.sub.2 are shifted in level at these level-shifting circuits 42.sub.1 and 42.sub.2 respectively, so that the resultant signals which are mutually opposite in phase and different in voltage level are output respectively from the output terminal 6.sub.1 connected to an interconnection point between a source of the n-channel type MOSFET N.sub.1 and the constant current source CS1.sub.1 and the output terminal 6.sub.2 connected to an interconnection point between a source of the n-channel type MOSFET N.sub.2 and the constant current source CS1.sub.2 and applied to the differential amplifier circuit 36 at its (+) and (-) inputs respectively.
If a level-shifting quantity for the signal applied to that differential amplifier circuit at its (+) input is idealistically the same as that for that opposite-phase signal applied at its (-) input and, at the same time, two signals mutually opposite in phase and different in voltage level which are output from the level-shifting circuit 42 are applied to the differential amplifier circuit 36 at its (+) and (-) inputs respectively, when a level of voltage applied to the (+) input is higher than that applied to the (-) input, the differential amplifier circuit 36 outputs a higher level of voltage and, when the level of voltage applied to the (+) input is lower than that applied to the (-) input, the differential amplifier circuit 36 outputs a lower level of voltage. Thus, the differential amplifier circuit 36 outputs binary signals which correspond to binary values represented by the two signals INA and INB mutually opposite in phase and different in voltage level which are input to the level-shifting circuits 42.sub.1 and 42.sub.2 at their respective input terminals 2.sub.1 and 2.sub.2. These binary signals are held in an idealistic time-wise relationship with the two input signals INA and INB which are mutually opposite in phase and different in voltage level; that is, since these binary signals have the same signal time-axis width as that for the signals INA and INB, they inflict no inconvenience on the CMOS internal circuit when it performs signal processing on them.
There is also provided another small-amplitude interface input circuit which uses the above-mentioned level-shifting circuit. An example of it is shown in FIG. 13.
This small amplitude interface output circuit 50 has roughly the same configuration as the small-amplitude interface input circuit 30 shown in FIG. 11.
The output circuit 50 shown in FIG. 13 is different from the input circuit 30 shown in FIG. 11 in that its level-shifting circuit 34 has its output terminals 6.sub.1 and 6.sub.2 connected to a load resistor 54 via a transmission line 52 and also in that in order to drive the load connected to a bus line at a high speed because of its being an output circuit, its transistors (e.g., n-channel type MOSFETs N.sub.1, N.sub.2, N.sub.3, and N.sub.4) have a large size and its constant current values (e.g., those for CS1.sub.1, CS1.sub.2, and 20) have a large magnitude.
With this, in FIG. 13 and other figures, like components are indicated by the same reference numerals, so that their description is omitted here.
The operations of the small-amplitude interface output circuit are also roughly the same as well.
That is, two signals INA and INB mutually opposite in phase and different in voltage level which are separately input at the input terminals 16 and 18 are amplified at the differential amplifier circuit 32 and applied to the gates of the respective n-channel type MOSFETs N1 and N.sub.2 of the level-shifting circuit 34. Respectively from the output terminals 6.sub.1 connected to an interconnection point between a source of the n-channel type MOSFET N.sub.1 and the constant current source CS1.sub.1 and the output terminal 6.sub.2 connected to an interconnection point between a source of the n-channel type MOSFET N.sub.2 and the constant current source CS1.sub.2 are output and respectively supplied to a load resistor 54 such signals mutually opposite in phase and different in voltage level which have been shifted in level by a predetermined quantity. The load resistor 54 is configured to operate normally when supplied with such a prescribed voltage level of signals.
Therefore, the load resistor 54 operates normally as far as the level-shifting quantity given by the level-shifting circuit is not affected by fluctuations in the process nor the temperature.
Note here that terms in Equation 3, particularly V.sub.T and .mu. will vary with fluctuations in the properties and the operating temperature during the manufacturing processes.
Supposing here that V.sub.IN =3.0V (V represent voltage value) and {2I.sub.DS /.beta.}.sup.1/2 =1V, and V.sub.T =0.5V in the conditions of certain manufacturing processes and operating temperature, EQU V.sub.OUT =3.0V-1.0V-0.5V=1.5V
is given (see FIG. 8A), while supposing the above-mentioned certain manufacturing process and operating temperature have changed to 0.8V from 0.5V of the V.sub.T value and to 0.8 times on the .mu. value, EQU V.sub.OUT =3.0V-1.12V-0.8V=1.08V,
is obtained (see FIG. 8B), so that these results cannot meet an originally expected operational requirement of the level-shifting circuit that even when the manufacturing process and the operating temperature have been changed, the same output voltage V.sub.OUT be obtained. That is, the level-shifting quantity for the output voltage V.sub.OUT varies.
Thus, the above-mentioned conventional level-shifting circuits have a disadvantage of not being capable of obtaining a predetermined level-shifting quantity.
Also, such a disadvantage may occur even with fluctuations in the supply voltage.
Since such a disadvantage is involved in the level-shifting circuit 1 shown in FIG. 7, the small-amplitude interface input circuit using this level shifting circuit 1 shown in FIG. 9 also has a problem due to fluctuations in the level-shifting quantity for the level-shifted signal output from the level-shifting circuit 1 which are caused by fluctuations in the manufacturing process, the operating temperature, and the supply voltage.
That is, if, caused by fluctuations in the manufacturing process, the operating temperature, and the supply voltage, the level-shifted signal rises in voltage level from V.sub.OUT 1S which has an appropriate level-shifting quantity of V.sub.OUT 1 shown in FIG. 10 up to V.sub.OUT 1U of V.sub.OUT 1 shown in the same figure, and is compared, as level-shifted, to the reference voltage V.sub.CP at the comparator 14, the comparator 14 outputs such a binary signal as represented by V.sub.OUT 2 (2) in FIG. 10.
As a result, thus output binary signal has a larger signal width than that of a normal signal width (i.e., V.sub.OUT 2 (1) in FIG. 10); that is, a skew occurs at the binary signal, thus causing the CMOS internal circuit 22 to malfunction when it has received this signal.
If, conversely, caused by fluctuations in the manufacturing process and the operating temperature, the level-shifted signal falls in voltage from V.sub.OUT 1S which has an appropriate level-shifting quantity of V.sub.OUT 1 shown in FIG. 10 down to V.sub.OUT 1D of V.sub.OUT 1 in the same figure and compared, as level-shifted, to the reference voltage VCP at the comparator 14, the comparator 14 outputs such a binary signal as represented by V.sub.OUT 2 (3) shown in FIG. 10.
As a result, thus output binary signal has a smaller signal width than that of a normal signal (i.e., V.sub.OUT 2 (1) in FIG. 10); that is, a skew occurs at the binary signal, thus also causing the CMOS internal circuit to malfunction.
The small-amplitude interface input circuits shown in FIGS. 11 and 12 also suffer from such a skew-related problem as having been described for the small-amplitude interface input circuit 10 shown in FIG. 9, i.e. a problem that fluctuations in the manufacturing process, the operating temperature, and the supply voltage bring about fluctuations in the level-shifting quantity for level-shifted signals output from the level-shifting circuit 1. Since in FIGS. 11 and 12 the following-stage is a differential amplifier circuit 36, it does not have such a skew as related to the reference level but does it have such a skew as caused by fluctuations in a so-called off-set voltage.
That is, when the manufacturing process, the operating temperature, or the supply voltage has changed, the resultant signal as level-shifted would rise or fall from a normal signal level.
In such a case, also in the small-amplitude interface input circuit 30 shown in FIG. 11 as well as in the small-amplitude interface input circuit 40 shown in FIG. 12, if there is no difference in terms of fluctuations in the level-shifting quantity between a signal level applied to the (+) input and the (-) input of the differential amplifier circuit 36, there is no difference either between a binary signal obtained by differential-amplifying at the differential amplifier circuit 36 those signals immediately after being level-shifted by a level-shifting quantity different from a normal level-shifting quantity and another binary signal obtained by differential-amplifying at the differential amplifier circuit 36 those signals immediately being level-shifted by the normal level-shifting quantity.
If, however, there occurs a difference in terms of level-shifting quantity between the level-shifting circuits 34.sub.1 and 34.sub.2 as well as between the level-shifting circuits 42.sub.1 and 42.sub.2, as mentioned above, there occurs a problem of not a skew caused by the reference but a skew caused by fluctuations in the offset voltage.
Therefore, there is brought about a disadvantage in that the CMOS internal circuit may malfunction when it has received such a binary signal as having a skew.
Moreover, the small-amplitude interface output circuit shown in FIG. 13 also suffers from such a problem that fluctuations in the level-shifting quantity may cause an output signal having a level-shifting quantity different from the normal level-shifting quantity to be output from the small-amplitude interface output circuit. If such a level-shifting quantity fluctuates, the small-amplitude interface input circuit 50 may malfunction which should operate normally when supplied with an input signal having a prescribed level-shifting quantity, which leads to another disadvantage.
To avoid such disadvantages, conventionally, values of the level-shifting quantity and an input voltage at which the following-stage circuit does not malfunction are obtained beforehand, so that such level-shifting values may be set not to permit that input voltage to be deviated. There are two methods for adjusting the level-shifting quantity for this purpose: a first method of adjusting a current Ids flowing through the constant current source and a second method of adjusting the value of .beta. of the n-channel type MOSFET N.sub.5. In order to increase the level-shifting quantity, for example by the first method, the drain current I.sub.DS may be increased and, by the second method, the value of a .beta. related term, for example, W may be decreased.
By the first method, whereby the effect of increases in I.sub.DS works in proportional to its square root, in order to roughly double the level-shifting quantity, the drain current I.sub.DS must be increased four times as much. This leads to another disadvantage of increasing power dissipation.
This changing method, therefore, is very disadvantageous in adopting in such a field as for example battery-driven integrated circuits, which are strongly required for saving on power dissipation.
By the second method, on the other hand, the output impedance of the n-channel MOSFET N.sub.5 is increased, thus deteriorating the high-speed performance, which leads to another disadvantage.
The second method, therefore, cannot be adopted in such integrated circuits which handle high-speed signals.
Thus, although the level-shifting quantity can be changed by either of these two changing methods, a problem of fluctuations in the level-shifting quantity caused by fluctuations in the manufacturing process, the operating temperature, or the supply voltage is still left unsolved.